1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory having a plurality of memory cell arrays which can perform a parallel operation in particular.
2. Description of the Related Art
There has been conventionally known an EEPROM in which information can be electrically reprogrammed as one of semiconductor memories. Among others, an NAND cell type EEPROM in which an NAND cell block is constituted by connecting a plurality of memory cells in series attracts attention as a memory which can be highly integrated (see, e.g., Japanese patent application laid-open No. 9-82923).
One memory cell of the NAND cell type EEPROM has an FET-MOS structure in which a floating gate (charge storage layer) and a control gate are laminated on a semiconductor substrate through an insulating film. Further, an NAND cell is constituted by connecting a plurality of memory cells in series in such a manner that a source and a drain are shared by adjacent memory cells, and this structure as one unit is connected to a bit line.
A memory cell array is constituted by arranging such NAND cells in a matrix form. The memory cell array is integrated and formed in a p type substrate or a p type well.
Drains of the NAND cells aligned in a column direction of the memory cell array on one end side are respectively connected to a bit line in common through a selection gate transistor, and sources on the other end side are respectively connected to a common source line through a selection gate transistor. A control gate of the memory transistor and a gate electrode of the selection gate transistor are connected in common in a row direction of the memory cell array as a control gate line (word line) and a selection gate line, respectively.
An operation of this NAND cell type EEPROM is as follows.
A data program operation is mainly performed from a memory cell provided at a position farthest from a bit line contact in sequence.
First, when the data program operation is started, 0V (“1”—data program bit line) or a power supply voltage Vcc (“0”—data program bit line) is given to the bit line in accordance with program data, and Vcc is supplied to the selection gate line on the bit line contact side. In this case, in a selected NAND cell connected to the “1”—data program bit line, a channel portion in the NAND cell is fixed to 0V through the selection gate transistor.
On the other hand, in the selected NAND cell connected to “1”—data program bit line, a channel portion in the NAND cell is charged to [Vcc−Vtsg (Vtsg is a threshold voltage of the selection gate transistor)] through the selection gate transistor and then enters a floating state. Subsequently, a control gate line of a selected memory cell in the selected NAND cell reaches 0V→Vpp (=approximately 20V: program high voltage), and any other control gate line in the selected NAND cell reaches 0V→Vmg (=approximately 10V: intermediate voltage).
In the selected NAND cell connected to the “1”—data program bit line, since the channel portion in the NAND is fixed to 0V, a large potential difference (=approximately 20V) is generated between the gate (=Vpp potential) and the channel portion (=0V) in the selected memory cell in the selected NAND cell, and electron injection occurs from the channel portion. As a result, a threshold value of the selected memory cell shifts in a forward direction, and programming of 1″—data is completed.
In the selected NAND cell connected to the “0”—data program bit line, a channel portion in the NAND is in a floating state. Therefore, a channel portion potential is increased from a [Vcc−Vtsg] potential to Vmch (=approximately 8V) while maintaining the floating state with an increase in a control gate line voltage (0V→Vpp, Vmg) due to an influence of capacitance coupling between the control gate line and the channel portion in the selected NAND gate. At this time, since a potential difference between the gate (=Vpp potential) and the channel portion of the selected memory cell in the selected NAND is relatively as small as approximately 12V, electron injection does not occur. Therefore, a threshold value of the selected memory cell does not vary and it is maintained in a negative state.
Data erasing is performed with respect to all the memory cells in the selected NAND cell block at the same time. That is, all the control gates in the selected NAND cell block are determined to have 0V, and a high voltage which is approximately 20V is applied to the bit line, the source line, the p type well (or the p type substrate), and the control gates and all the selected gates in a non-selected NAND cell block. As a result, electrons of the floating gates in all the memory cells in the selected NAND cell block are discharged to the p type well (or the p type substrate), and the threshold voltage is shifted in a negative direction.
A data read operation is carried out by detecting whether a current flows through a selected memory cell provided that the control gates of the selected memory cell are determined to have 0V and the control gates and the selected gate of any other memory cells are determined to have a read intermediate voltage Vread (≦4V).
Such an NAND cell type EEPROM usually has a function to output a Pass/Fail signal indicative of whether an operation such as programming or erasing has attained success or failed after completion of this operation. That is, for example, after a program/erase operation is terminated, when a command to output the Pass/Fail signal to the outside of a chip is inputted, the Pass/Fail signal is outputted from an I/O pad.
Further, as shown in FIG. 1, the NAND type EEPROM in recent years has a plurality of memory cell arrays Array0, Array1, Array2 and Array3 in one chip, and is constituted in such a manner that the plurality of memory cell arrays Array0, Array1, Array2 and Array 3 are operated in parallel in order to realize a high-speed operation.
In this case, to the NAND type EEPROM is added a function to output the Pass/Fail signal indicative of whether, e.g., a program/erase operation has attained success with respect to all the memory cell arrays after the program/delete operation is terminated or whether the program/erase operation has failed with respect to at least one memory cell array, i.e., the Pass/Fail signal of the entire chip. Furthermore, there is added a function to output a plurality of Pass/Fail signals indicative of whether the program/erase operation has attained success or failed with respect to each of the plurality of memory cell arrays, i.e., a Pass/Fail signal for each memory cell array.
Table 1 shows an example of allocation of the Pass/Fail signal to data input/output terminals I/O 0 to I/O 7 in the non-volatile semiconductor memory depicted in FIG. 1.
TABLE 1(a) com-ASTATUSOUTPUTI/O0Chip Status-IPass → 0 Fail → 1I/O1Not Used0I/O2Not Used0I/O3Not Used0I/O4Not Used0I/O5Not Used0I/O6Ready/BusyBusy → 0 Ready → 1I/O7Write ProtectProtect → 0 Not Protect → 1
TABLE 2(b) com-BSTATUSOUTPUTI/O0Chip Status-IPass → 0 Fail → 1I/O1Array (0)Pass → 0 Fail → 1I/O2Array (1)Pass → 0 Fail → 1I/O3Array (2)Pass → 0 Fail → 1I/O4Array (3)Pass → 0 Fail → 1I/O5Not Used0I/O6Ready/BusyBusy → 0 Ready → 1I/O7Write ProtectProtect → 0 Not Protect → 1
As apparent from Table 1 and Table 2, the non-volatile semiconductor memory usually has a function (Table 1) to output the Pass/Fail signal of the entire chip as well as a function (Table 2) to output the Pass/Fail signal for each memory cell array.
Moreover, in order to realize, e.g., the function of Table 1, supplying a command com-A to the chip can suffice. Additionally, in order to realize the function of Table 2, supplying a command com-B to the chip can suffice.
Meanwhile, as shown in FIG. 1, when one chip is enough for a memory capacity required for a package product (package product=1 gigabit, memory chip capacity=1 gigabit), only one chip is usually put in the package product. However, as shown in FIG. 2, when one chip is not enough for a memory capacity required for a package product (package product=2 gigabit, memory chip capacity=1 gigabit), a plurality of chips, which is two chips in this example, must be put in the package product.
Further, allocation of the Pass/Fail signal to the data input/output terminals I/O 0 to I/O 7 in the non-volatile semiconductor memory depicted in FIG. 2 is as shown in Table 1 and Table 2 like the semiconductor memory illustrated in FIG. 1.
That is, two chips are selected based on chip addresses. Furthermore, an output operation of the Pass/Fail signal is executed with respect to the selected chip under statuses based on Table 1 or Table 2.
When chips used in the package products shown in FIGS. 1 and 2 are determined as the first generation, the second generation chips usually have a memory capacity which is twofold or above of the memory capacity of the first generation due to a reduction in design rule or the like. Therefore, for example, when the second generation chip is used in the package product shown in FIG. 2, putting only one chip in the package product can suffice, thereby reducing a chip cost.
However, the conventional non-volatile semiconductor memory has two types of output mode of the Pass/Fail signal, i.e., an output mode of the Pass/Fail signal of the entire chip and an output mode of the Pass/Fail signal for each memory cell array. This is the same even though the generation of the memory chip advances. On the other hand, when the generation of the memory chip advances one step, the number of memory cell arrays which are arranged in one chip and can perform a parallel operation doubles or more.
Therefore, for example, in output of the Pass/Fail signal for each memory cell array with respect to the second generation chip, allocation of the Pass/Fail signal for the first generation chip such as shown in Table 2 to the data input/output terminals I/O 0 to I/O 7 cannot be used as it is.
Therefore, since a system which outputs the Pass/Fail signal in the second generation chip is different from the counterpart in the first generation chip, the memory chip cannot be simply replaced from the first generation to the second generation with respect to the same package product.
As described above, replacing the chip used in the same package product from the first generation to the second generation is very effective in order to reduce a chip cost in the prior art. However, since there is no compatibility between the system which outputs the Pass/Fail signal in the first generation chip and the system which outputs the Pass/Fail signal in the second generation chip, there is a problem that replacing the chip used in the same package product from the first generation to the second generation is difficult.
Therefore, in regard to the system which outputs the Pass/Fail signal, there have been demanded a facilitation of replacement from the precedent generation chip to the next generation chip with respect to the same package product and a reduction in a chip cost by giving the compatibility between the precedent generation chip and the next generation chip.